MDIS=INDIVIDUAL_USE_THE_, CR=CLEAR_RESET_, PWMEN=TIMER_MODE_IS_ENABLE, CE=THE_COUNTERS_ARE_DIS
Timer Control Register. The TCR is used to control the Timer Counter functions.
| CE | Counter Enable 0 (THE_COUNTERS_ARE_DIS): The counters are disabled. 1 (THE_PWM_TIMER_COUNTE): The PWM Timer Counter and PWM Prescale Counter are enabled for counting. |
| CR | Counter Reset 0 (CLEAR_RESET_): Clear reset. 1 (THE_PWM_TIMER_COUNTE): The PWM Timer Counter and the PWM Prescale Counter are synchronously reset on the next positive edge of PCLK. The counters remain reset until this bit is returned to zero. |
| RESERVED | Reserved. Read value is undefined, only zero should be written. |
| PWMEN | PWM Enable 0 (TIMER_MODE_IS_ENABLE): Timer mode is enabled (counter resets to 0). 1 (PWM_MODE_IS_ENABLED_): PWM mode is enabled (counter resets to 1). PWM mode causes the shadow registers to operate in connection with the Match registers. A program write to a Match register will not have an effect on the Match result until the corresponding bit in PWMLER has been set, followed by the occurrence of a PWM Match 0 event. Note that the PWM Match register that determines the PWM rate (PWM Match Register 0 - MR0) must be set up prior to the PWM being enabled. Otherwise a Match event will not occur to cause shadow register contents to become effective. |
| MDIS | Master Disable (PWM0 only). The two PWMs may be synchronized using the Master Disable control bit. The Master disable bit of the Master PWM (PWM0 module) controls a secondary enable input to both PWMs, as shown in Figure 141. This bit has no function in the Slave PWM (PWM1). 0 (INDIVIDUAL_USE_THE_): Individual use. The PWMs are used independently, and the individual Counter Enable bits are used to control the PWMs. 1 (MASTER_USE_PWM0_IS_): Master use. PWM0 is the master, and both PWMs are enabled for counting. |
| RESERVED | Reserved. Read value is undefined, only zero should be written. |